Fujitsu FR60 Hardware Manual page 596

CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS
■ FRLR: Instruction RAM Limit Control Register (F-Bus RAM Limit Control Register)
The configuration of the instruction RAM limit control register is shown below:
Address : 00000280
Initial value
[Bits 7 to 2] Reserved bits
These bits are reserved bits. If writing data to these bits, be sure to write "0". The values read from these
bits are undefined.
[Bits 1, 0] FL1 and FL0
These bits limit the RAM area available for executing instructions.
FL1
0
0
1
1
Note:
Do not set a value that exceeds the RAM capacity installed on the device. If the setting is rewritten,
insert at least one NOP instruction immediately after that processing.
578
7 6 5
- - -
H
- - -
FL0
0 (Setting not allowed)
1 The 4K bytes area at addresses 3F000
0 The 8K bytes area at addresses 3E000
1 The 16K bytes area at addresses 3C000
4 3 2 1
- - - FL1
- - - 0
Explanation
to 3FFFF
H
to 3FFFF
H
to 3FFFF
H
0
FL0 (R/W)
1
can be used (initial value).
H
can be used.
H
can be used.
H