Fujitsu FR60 Hardware Manual page 131

[Bit 13] WDOG (WatchDOG reset occurred)
This bit indicates whether a reset (INIT) occurred due to the watchdog timer.
Value
0 No INIT occurred due to the watchdog timer.
1 INIT occurred due to watchdog timer.
• This bit is initialized to "0" after a reset (INIT) due to INIT pin input or just after it is read.
• This bit is readable; writing to the bit has no effect on the bit value.
[Bit 12] (Reserved bit)
This bit is reserved.
[Bit 11] SRST (Software ReSeT occurred)
This bit indicates whether a reset (RST) occurred due to writing to the SRST bit of the STCR register (a
software reset).
Value
0 No RST occurred due to a software reset.
1 RST occurred due to a software reset.
• This bit is initialized to "0" after a reset (INIT) due to INIT pin input or just after it is read.
• This bit is readable; writing to the bit has no effect on the bit value.
[Bit 10] (Reserved bit)
This bit is reserved.
[Bits 9, 8] WT1, WT0 (Watchdog interval Time select)
This bit sets the interval of the watchdog timer.
The values written to these bits determine the interval of the watchdog timer, which can be selected
from the four types shown in the following table.
Minimum required interval for writing
WT1 WT0 to the WPR to suppress a watchdog
0 0
0 1
1 0
1 1
φ: Frequency of the system base clock
• These bits are initialized to "00" after a reset (RST).
• These bits are readable, but are writable only once after a reset (RST). Any further writing is disabled.
Explanation
Explanation
reset
φ x 2 16
(initial value)
φ x 2 18
φ x 2 20
φ x 2 22
Time from writing the last 5AH to the
WPR until a watchdog reset occurs
φ x 2 16 to φ x 2
φ x 2 18 to φ x 2
φ x 2 20 to φ x 2
φ x 2 22 to φ x 2
17
19
21
23
113