Fujitsu FR60 Hardware Manual page 189

ASZ[3:0] are used to set the size of each area by modifying the number of bits for address comparison to a
value different from ASR. Thus, an ASR contains bits that are not compared.
Bits ASZ[3:0] of ACR0 are initialized to 1111
just after RST is executed is specially set from 00000000
entire-area setting is reset after the first write to ACR0 and an appropriate size is set as indicated in Table
4.2-1 .
[Bits 11 to 10] DBW[1:0] (Data Bus Width [1:0])
These bits set the data bus width of each chip select area as indicated in the following table:
DBW1 DBW0
0 0
0 1
1 0
1 1
The same values as those of the WTH bits of the mode vector are written automatically to bits DBW[1:0]
of ACR0 during the reset sequence.
[Bits 9 to 8] BST[1:0] (Burst Size [1:0])
These bits set the data bus width of each chip select area as indicated in the following table:
BST1 BST0
0 0
0 1
1 0
1 1
In areas for which a burst length other than the single access is set, continuous burst access is performed
within the address boundary determined by the burst length only when prefetch access is performed or data
having a size exceeding the bus width is read.
The maximum burst length of the bus width 32-bit area must be set to four bursts or less. Setting of two
bursts or less is recommended.
Fujitsu recommends setting no more than two bursts for the maximum burst length of the bus width 16-bit
area.
RDY input is ignored in areas for which any burst length other than the single access is set.
(0F ) by RST. Despite this setting, however, the CS0 area
B H
H
8 bits (byte access)
16 bits (halfword access)
Reserved Setting disabled
Reserved Setting disabled
Maximum burst length
1 (single access)
2 bursts (address boundary: 1 bit)
4 bursts (address boundary: 2 bits)
8 bursts (address boundary: 3 bits)
to FFFFFFFF (setting of entire area). The
H
Data bus width
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