Fujitsu FR60 Hardware Manual page 438

CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE
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External shift clock mode
In external shift clock mode, data is transferred at a rate of 1 bit per clock pulse in synchronization with the
external shift clock input via the SCK pin. The transfer speed can be set in a range from DC to 1/(8
peripheral system clock cycles). For example, the transfer speed can be up to 3.125 MHz when 1 peripheral
system clock cycle is 0.04 µs.
Data can also be transferred at a rate of bits per instruction when the settings below are made.
Select external shift clock mode, and write "0" to the bit corresponding to the SCK pin of the port function
register (PFR). Write "1" to the direction register for the port sharing the SCK pin to set the port to output
mode. After the above setting, when "1" and "0" are written to the port data register (PDR) for the port, the
port value output via the SCK pin is fetched as the external clock and transfer operation is performed.
Be sure to start the shift clock at the "H" level.
Note:
The SMCS or SDR must not be written to during serial I/O operation.
■ States of Serial I/O Interface Operation
There are four serial I/O operation status: STOP, halt, SDR R/W standby, and transfer.
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STOP
The STOP state is initiated upon RESET or when "1" is written to the STOP bit of SMCS. The shift
counter is initialized, and "0" is written to SIR.
To resume operation from the STOP state, write "0" to STOP and "1" to STRT. (These two bits can be
written to simultaneously.) Since the STOP bit overrides the STRT bit, transfer cannot be started by writing
"1" to STRT while "1" is written to STOP.
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Halt
When transfer is completed while the MODE bit is "0," "0" is set to BUSY and "1" is set to SIR of the
SMCS, the counter is initialized, and the system stops. To resume operation from the stop state, write "1" to
STRT.
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Serial data register R/W standby
When serial transfer is completed while the MODE bit of the SMCS register is "1", the BUSY and SIR bits
of the SMCS register are set to "0" and "1", respectively, and the SIO enters the serial data register R/W
standby state. If the interrupt enable register is set, an interrupt signal is output from the SIO.
To resume operation from the serial data register R/W standby state, data must be read from or written to
the serial data register. The BUSY bit is set to "1", and transfer operation starts.
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Transfer
"1" is set to the BUSY bit and serial transfer is being performed. According to the MODE bit, the halt state
or R/W standby state comes next.
Figure 14.2-2 shows the transitions between the operating states.
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