Fujitsu FR60 Hardware Manual page 140

CHAPTER 3 CPU AND CONTROL UNITS
[Bit 10] PLL1EN (PLL1 ENable)
This bit is the enable bit of the main PLL.
Rewriting of this bit is not allowed while the main PLL is selected as the clock source.
In addition, selecting the main PLL as the clock source is not allowed while this bit is 0 (bits 9 and 8:
Determined from the settings of the CLKS1 and CLKS0 bits).
The main PLL stops in stop mode even when this bit is set to "1" as long as STCR bit 0 (OSCD1) is set
to "1". After the device returns from the stop mode, the main PLL is enabled again.
Value
0
1
• This bit is initialized to "0" by a reset (INIT).
• This bit is readable and writable.
122
Main PLL stopped (initial value)
Main PLL enabled
Explanation