Fujitsu FR60 Hardware Manual page 649

Initializing
Initializing the Divide-By Rate .......................... 110
Input Capture
16-bit Input Capture Operation .......................... 430
External Input Pin Corresponding to Each Input
Capture Channel ................................. 426
Input Capture Block Diagram............................ 427
Input Capture Data Register (IPCP0 to IPCP3)
.......................................................... 428
Overview of the Input Capture Module .............. 425
Input Capture Control Register
Input Capture Control Registers
(ICS01 and ICS23).............................. 428
Input Capture Data Register
Input Capture Data Register (IPCP0 to IPCP3)
.......................................................... 428
Input Capture Module Register
Input Capture Module Registers ........................ 426
Input Select
[Bits 28 to 24] IS4 to 0 (Input Select):
Transfer Source Selection .................... 478
Input Timing
Input Timing for 16-bit Input Capture ................ 430
Input-Output Circuit
Input-Output Circuit Types ................................. 27
Instruction
Block Diagram of the Data Internal RAM/
Instruction Internal RAM Access Restriction
Functions ........................................... 576
Branch Instructions with Delay Slot..................... 68
Data Internal RAM/Instruction Internal RAM Access
Restriction Function Registers.............. 576
FRLR: Instruction RAM Limit Control Register
(F-Bus RAM Limit Control Register)
.......................................................... 578
How to Read the Instruction Lists...................... 603
Instruction Format............................................ 605
Instructions not Using a Delay Slot ...................... 71
Operation of INT Instruction ............................... 87
Operation of INTE Instruction............................. 87
Operation of RETI Instruction ............................. 89
Operation of the Data Internal RAM/
Instruction Internal RAM Access Restriction
Functions ........................................... 579
Operation of Undefined Instruction Exception ...... 88
Other Types of Instructions ................................. 54
Overview of Branch Instructions ......................... 67
Instruction RAM Limit Control Register
FRLR: Instruction RAM Limit Control Register
(F-Bus RAM Limit Control Register)
.......................................................... 578
INT
Operation of INT Instruction ............................... 87
INTE
Operation of INTE Instruction............................. 87
Internal Architecture
Features of the Internal Architecture.....................50
Overview of Internal Architecture ........................49
Structure of the Internal Architecture....................51
Internal Memory
Internal Memory...................................................3
Internal Operating Clock
Generation of Internal Operating Clock ..............104
Internal RAM
Internal RAM .....................................................35
Internal RAM Access Restriction
Block Diagram of the Data Internal RAM/
Instruction Internal RAM Access Restriction
Functions ............................................576
Internal-ROM
Bus Mode 1 (Internal-ROM/External-bus Mode)
............................................................91
Interrupt
Bit Configuration of Enable Interrupt Request
Register (ENIRn).................................345
Bit Configuration of External Level Register (ELVRn)
..........................................................347
Bit Configuration of the External Interrupt Request
Register (EIRRn) .................................346
Bit Configuration of the Interrupt Control Register
(ICR)..................................................329
Block Diagram of the Delayed Interrupt Module
..........................................................353
Block Diagram of the External Interrupt and
NMI Controller....................................343
Block Diagram of the Interrupt Controller...........327
Configuration of Interrupt Control Register (ICR)
............................................................75
Delayed Interrupt Module Register (DICR: Delayed
Interrupt Module Register) ...................354
Details of the Interrupt Controller Registers ........328
Details of the Registers for the External Interrupt and
NMI Controller....................................344
DMA Transfer and Interrupts.............................506
DMAC Interrupt Source Clear Register (SRCL)
..........................................................418
EIT Interrupt Levels............................................73
External Interrupt and NMI Controller
Registers.............................................342
External Interrupt Request Level ........................349
Hardware Configuration of the Interrupt
Controller ...........................................324
Interrupt Controller ...............................................4
Interrupt Function .............................................424
Interrupt Generation Timing ..............................267
Interrupt Level Mask (ILM) Register....................74
Interrupt Number ..............................................355
Interrupt Processing ..........................................470
Interrupt Sources and Timing Chart....................318
Interrupt Stack....................................................78
Interrupt Vectors ..............................................594
INDEX
631