Fujitsu FR60 Hardware Manual page 300

CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER
[Bit 5] IVFE
This bit is the interrupt enable bit for the 16-bit free-running timer.
An interrupt is generated when the IVFE bit is "1" and the interrupt flag (bit 6 [IVF]) is set to "1".
IVFE
[Bit 4] STOP
This bit is used to stop the counting operation of the 16-bit free-running timer.
Writing "1" to the STOP bit stops the counting operation of the 16-bit free-running timer.
Writing "0" to the STOP bit starts the counting operation of the 16-bit free-running timer.
STOP
Note:
When the 16-bit free-running timer is stopped, the output compare operation is also stopped.
[Bit 3] MODE
This bit is used to set the initialization condition for the 16-bit free-running timer.
When the MODE bit is "0", the counter value can be initialized by a reset or the clear bit (bit 2 [CLR]).
When the MODE bit is "1", the counter value can be initialized by a reset, the clear bit (bit 2 [CLR]), or
matching of the values of the counter and output compare register 0.
MODE
Note:
The counter value is initialized at the exact point at which the count value changes.
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0 Interrupts disabled (initial value)
1 Interrupts enabled
0 Counting enabled (started; initial value)
1 Counting disabled (stopped)
0 Initialization by reset or clear bit (initial value)
1 Initialization by reset, clear bit, or compare register 0
Interrupt enable
Counting operation
Counter initialization