Fujitsu FR60 Hardware Manual page 137

[Bit 8] SYNCS (SYNChronous Standby enable)
This bit is the synchronous standby enable bit.
It is used to select one of the following operations, which is to be used if an standby request (either
sleep or stop mode request) occurs: (1) Performing a normal standby operation only by writing to the
control bit in the STCR register or (2) performing a synchronous standby operation by reading the
STCR register after writing to the control bit in the STCR register.
Value
0
1
• This bit is initialized to "0" by a reset (INIT).
• This bit is readable and writable.
■ Timebase Counter Clear Register (CTBR)
The configuration of the timebase counter clear register is shown below:
The timebase counter clear register initializes the timebase counter.
If {A5 } and {5A
H
to "0" as soon as {5A
if data other than {5A
written. Otherwise, a clear operation will not occur.
The value read from this register is undefined.
Note:
If the timebase counter is cleared using this register, the oscillation stabilization wait interval,
watchdog timer interval, and timebase timer interval temporarily vary.
Normal standby operation (initial value)
Synchronous standby operation
bit 7
Address: 00000483
D7
H
W
Initial value (INIT) X
Initial value (RST) X
} are written successively to this register, all the bits in the timebase counter are cleared
H
} is written. There is no time limit between writing of {A5
H
} is written after {A5
H
Explanation
6 5 4 3
D6 D5 D4 D3
W W W W
X X X X
X X X X
} is written, {A5 } must be written again before {5A
H H
2 1 0
D2 D1 D0
W W W
X X X
X X X
} and {5A }. However,
H H
H
119
} is