Fujitsu FR60 Hardware Manual page 229

■ CS Delay Setting (TYP[3:0]=0000
Figure 4.5-7 shows setting of a CS delay.
MCLK
A[23:0]
AS
CSn
RD
READ
D[31:16]
WRn
WRITE
D[31:16]
• If the W02 bit is "1", assertion starts in the cycle following the cycle in which AS is asserted. For
successive accesses, a negation period is inserted.
, AWR=000C
B
Figure 4.5-7 Setting of CS Delay
)
H
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