Fujitsu FR60 Hardware Manual page 418

CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE
■ Asynchronous (Start-stop Synchronization) Mode
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Transfer data format
UART handles only data in the NRZ (Non Return to Zero) format. Figure 14.1-2 shows the data format.
SI,SO
As shown in Figure 14.1-2 , the transfer of data always starts with the start bit ("L" level data), continues as
long as the data bit length specified in LSB First, and ends with a stop bit ("H" level data). If an external
clock is selected, you always must input a clock.
The data length can be set to 7 or 8 bits in normal mode (Mode 0), but must be set to 8 bits in
multiprocessor mode (Mode 1). In multiprocessor mode, no parity can be added; instead, the A/D bit is
always added.
●
Receive operation
If the RXE bit (Bit 1) of the SCR register is set to "1", a receive operation is always in progress.
If a start bit appears on the receive line, one-frame data is received according to the data format specified in
the SCR register. If an error occurs after reception of one frame is completed, the error flag is set and then
the RDRF flag (Bit 4 of the SSR register) is set. If, at this time, the RIE bit (Bit 1) of the same SSR register
is set to "1", a receive interrupt is generated for the CPU. Check the flags of the SSR register and read the
SIDR register if normal reception has occurred or perform the necessary processing if an error has
occurred.
The RDRF flag is cleared when the SIDR register is read.
●
Send operation
If the TDRE flag (Bit 3) of the SSR register is set to "1", send data is written to the SODR register. If, at
this time, the TXE bit (bit 0) of the SCR register is set to "1", transmission occurs.
The TDRE flag is set again when the data set in the SODR register is loaded into the send shift register and
begins to be transferred, indicating that the next send data can be set. If, at this time, the TIE bit (bit 0) of
the same SSR register is set to "1", a send interrupt requesting that the send data be set in the SODR
register is generated for the CPU.
The TDRE flag is cleared if data is set in the SODR register.
400
Figure 14.1-2 Transfer Data Format (Modes 0 and 1)
0 1 1 1
LSB
Start
Data that has been transferred is 01001101
0 0 1 0 1 1
MSB Stop
A/D Stop
.
B
(Mode 0)
(Mode 1)