Fujitsu FR60 Hardware Manual page 283

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Count clear/gate function
The ZIN pin can be used after selecting the count clear function or gate function based on the CGSC bit of
the CCR register.
When the count clear function is started, the ZIN pin clears the counter. The CGE1 and CGE0 bits of the
CCRL register can control which edge input of the ZIN pin to use for clearing the counter.
When the gate function is started, the ZIN pin enables or disables counting. The CGE1 and CGE0 bits of
the CCR register can control which level input of the ZIN pin enables counting.
This function is effective for all modes.
Table 6.1-4 summarizes how the ZIN pin functions are selected.
Table 6.1-4 Selecting the ZIN Pin Function
CGSC
0
1
CGE1, CGE0
00
B
01
B
10
B
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Count direction flag
The count direction flag (UDF1 and UDF0) indicates at the time of up/down counting whether the counting
operation preceding the current operation was counting up or down. Based on the count clock signal from
the input of the AIN and BIN pins, this value of this flag changes for each count.
By checking this flag, the current rotation direction can be determined by such as motor.
Table 6.1-5 summarizes how the count direction flag works.
Table 6.1-5 Count Direction Flag
UDF1, UDF0
01
B
10
B
11
B
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Count direction change flag
The CDCF is set when the counting direction changes between up and down. Simultaneously to setting this
flag, an interrupt request to the CPU can be generated. By referring the interrupt and count direction flag,
ZIN pin function
Counter clear function
Gate function
When counter clear function is
Disables detection.
Rising edge
Falling edge
Down count
Up count
Up/down occurs simultaneously (no counting operation is performed).
When gate function is used
used
Disables detection.
"L" level
"H" level
Count direction
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