Fujitsu FR60 Hardware Manual page 69

■ Structure of the Internal Architecture
The FR CPU uses the Harvard architecture, in which the instruction bus and data buses are independent of
each other.
A 32-bit ↔ 16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interface between the
CPU and peripheral resources.
A Harvard ↔ Princeton bus converter is connected to the I-bus and D-bus to provide an interface between
the CPU and the bus controller.
Figure 3.2-1 shows the structure of the internal architecture.
Data
RAM
32-bit
16-bit
Bus converter
R-bus
Peripheral resources
Figure 3.2-1 Structure of the Internal Architecture
D-bus
I address
D address
D data
Address
Data
16
Internal I/O
FRex CPU
I-bus
32
32
I data
32
32
32
32
F-bus
Bus converter
External address
Harvard
24
External data
16
Princeton
bus
converter
51