Fujitsu FR60 Hardware Manual page 509

[Bit 28] PM01 (Priority mode ch0,1 robin): Channel priority rotation
This bit is set to alternate priority for each transfer between Channel0 and Channel1.
PM01
0
1
• When reset: Initialized to "0".
• This bit is readable and writable.
[Bits 27 to 24] DMAH (DMA Halt): DMA temporary stop
These bits control temporary stopping of all DMA channels. If these bits are set, DMA transfer is not
performed on any channel before these bits are cleared.
When DMA transfer is activated after these bits are set, all channels remain temporarily stopped.
Transfer requests that occur on channels for which DMA transfer is enabled (DENB=1) while these bits
are set are all enabled. The transfer can be started by clearing all these bits.
Other than 0000
• When reset: Initialized to "0".
• These bits are readable and writable.
[Bits 30, 29, and 23 to 0] (Reserved): Unused bits
• A read value is undefined.
■ Other Functions
The MB91350A has the DACK, DEOP, and DREQ pins, which can be used for external transfer. These
pins can also be used as general-purpose ports.
To use the DACK, DEOP, and DREQ pins for external transfer, their operation mode must be switched
from the port function to the DMA pin function.
To make the switch, set the PFR register.
Note:
The MB91F353A/351A/352A/353A do not have an external interface.
Fixes the priority. ( ch0 > ch1 )(initial value)
Alternates priority. ( ch1 > ch0 )
DMAH
0000 Enables the DMA operation on all channels. (initial value)
Temporarily stops DMA operation on all channels.
Function
Function
491