Fujitsu FR60 Hardware Manual page 464

2
CHAPTER 15 I C INTERFACE
[Bit 4] LRB (Last Received Bit)
This bit is an acknowledge storage bit that stores an acknowledge from the receiving device.
Value
0
1
This bit is rewritten if an acknowledge is detected (reception 9 bits). This bit is cleared if a START or
STOP condition is detected.
[Bit 3] TRX (Transferring Data)
This bit indicates the transmission status during a data transfer.
Value
0
1
This bit is set to "1" if:
A START condition occurs in master mode.
Transfer of the first byte ends during read access (transmission) in slave mode.
Data is being sent in master mode.
This bit is set to "0" if:
The bus is idle (IBCR BB=0).
An arbitration loss occurs.
"1" is written to the SCC bit in the mask interrupt status (MSS=1, INT=1).
The MSS bit is cleared in the mask interrupt status (MSS=1, INT=1).
No acknowledge occurred for the last transfer byte in slave.
Data is received in slave mode.
Data is received from a slave in master mode.
[Bit 2] AAS (Addressed As Slave)
This bit is the slave addressing detection bit.
Value
0
1
This bit is cleared when a (repeated) START or STOP condition is detected.
This bit is set when a 7-bit or 10-bit slave address is detected.
446
Slave acknowledge detected
Slave acknowledge not detected
Data transmission stopped
Data transmission in progress
The interface is not specified as a slave.
The interface is specified as a slave.
Function
Function
Function