Fujitsu FR60 Hardware Manual page 271

[Bit 13] CFIE: Count direction change interrupt enable bit
This bit controls the interrupt output for the CPU when CDCF is set. An interrupt occurs if the count
direction is changed at least once during counting.
CFIE
0 Disables direction change interrupt output (initial value).
1 Enables direction change interrupt output.
[Bit 12] CLKS: Internal prescaler selection bit
When timer mode is selected, this bit selects the frequency of the internal prescaler.
This bit is effective only in timer mode and only for down counting.
CLKS
0 2 machine cycles (initial value)
1 8 machine cycles
[Bits 11 and 10] CMS1 and CMS0: Counting mode selection bit
These bits select counting mode.
CMS1 CMS0
0 0
0 1
1 0
1 1
[Bits 9 and 8] CES1 and CES0: Count clock edge selection bit
In up/down counting mode, these bits select the input of internal circuit and detection edge of external
pins AIN and BIN.
This setting is invalid in modes other than up or down counting mode.
CES1 CES0
0 0
0 1
1 0
1 1
[Bit 7] (reserved)
This bit is reserved. This bit must always be set to "0".
Direction change interrupt output
Selected internal clock
Timer mode [down count] (initial value)
Up or down counting mode
Phase difference counting mode, 2 multiplication
Phase difference counting mode, 4 multiplication
Disables edge detection (initial value).
Detects falling edge.
Detects rising edge.
Detects rising and falling edges.
Counting mode
Selection edge
253