Fujitsu FR60 Hardware Manual page 653

Output Compare Module Register
Output Compare Module Registers .................... 432
Output Control Register
Output Control Register (OCS0 to OCS7) .......... 434
Output Pin
Output Pin Function ......................................... 294
Overall Configuration
Block Diagram of the PPG Timer (Overall
Configuration and One Channel) .......... 300
Overview
Overview of Branch Instructions ......................... 67
Overview of Byte Ordering ............................... 188
Overview of Device State Control ..................... 133
Overview of DMA External Interface
Operation ........................................... 529
Overview of DMAC......................................... 492
Overview of Flash Memory Registers ................ 539
Overview of Flash Memory Write/Erase ............ 557
Overview of Internal Architecture ....................... 49
Overview of Little Endian Method..................... 197
Overview of Operating Modes ............................ 90
Overview of Reset (Device Initialization)............. 94
Overview of Serial I/O Interface (SIO)
Operation ........................................... 419
Overview of the 16-bit Free-running Timer ........ 278
Overview of the 16-bit Reload Timer ................. 286
Overview of the 8/16-bit Up/Down
Counters/Timers ................................. 246
Overview of the A/D Converter Registers .......... 364
Overview of the Bit Search Module ................... 356
Overview of the Data Registers
(ADTHx and ADTLx) ......................... 375
Overview of the Delayed Interrupt Module......... 352
Overview of the DMAC Registers ..................... 473
Overview of the Flash Memory Automatic
Algorithm........................................... 547
2
Overview of the I C Interface Registers ............. 444
Overview of the Input Capture Module .............. 425
Overview of the Output Compare Module .......... 431
Overview of the Serial I/O Interface (SIO) ......... 410
Overview of the UART .................................... 386
Overview of the U-TIMER ............................... 268
Register Overview of External Bus Interface ...... 167
P
Package Dimension
MB91F353A/351A/352A/353A Package Dimensions
............................................................ 10
MB91F355/354A/355A/F356B/F357B Package
Dimensions (Reference Diagram) ............. 9
PC
PC (Program Counter) ........................................ 61
PCR
Pull-up Control Registers (PCR)........................ 236
PCSR
Configuration of PPG Cycle Setting Register
(PCSR) ...............................................307
PDR
Port Data Registers (PDR) .................................234
PDUT
Configuration of PPG Duty Setting Register
(PDUT) ..............................................308
Peripheral Circuit
Transfer Stop Requests from Peripheral
Circuits...............................................513
Peripheral Clock
Peripheral Clock (CLKP) ..................................109
Peripheral Resource
Correspondence between the Memory Space Area and
Peripheral Resource Registers ...............583
Peripheral Stop Control
Block Diagram of Peripheral Stop Control ..........155
Peripheral Stop Control Register
Detailed Explanation of the Peripheral Stop Control
Registers.............................................156
List of Peripheral Stop Control Registers ............155
PFR
Port Function Registers (PFR) ...........................237
PFRs
Initial Values and Functions of the Port Function
Registers (PFRs)..................................238
Pin Function
List of Pin Functions ...........................................13
Pin Layout
Pin Layout of the MB91F353A/351A/352A/353A
............................................................12
Pin Layout of the MB91F355A/354A/355A/
F356B/F357B........................................11
Pin State
Explanation of Terms Used in the Pin State
Lists ...................................................597
Pin States in Each CPU State .............................598
PLL
PLL Operation Enable.......................................105
Wait Time after Enabling a PLL ........................106
PLL Clock Mode
Note on Operating in PLL Clock Mode.................33
PLL Multiply-by Rate
PLL Multiply-by Rate .......................................105
Wait Time after Changing the PLL Multiply-by
Rate....................................................106
Port Data Register
Port Data Registers (PDR) .................................234
Port Function Register
Initial Values and Functions of the Port Function
Registers (PFRs)..................................238
Port Function Registers (PFR) ...........................237
INDEX
635