Fujitsu FR60 Hardware Manual page 159

[Sources of return from the stop state]
• Generation of a specific valid interrupt request (not requiring a clock)
Only the external interrupt input pins (INTn pins), main clock oscillation stabilization wait timer
interrupt during main clock oscillation, and watch interrupt during subclock oscillation are enabled.
If an interrupt request with an interrupt level other than interrupt disabled (1F
cleared and the RUN state (normal operation state) is entered.
To prevent stop mode from being cleared even when an interrupt request occurs, set interrupt disabled
(1F
H
• Watch timer interrupt
If a watch timer interrupt request occurs when standby control register (STCR) bit 1 (OSCD2 bit) is set
to "0", stop mode is cleared and the RUN state (normal operation) is entered.
To prevent stop mode from being cleared even when an interrupt request occurs, set the interrupt enable
bit of the watch timer to interrupt disabled.
• Main clock oscillation stabilization wait timer interrupt
If a main clock oscillation stabilization wait timer interrupt request occurs when oscillation control
register (OSCCR) bit 0 (OSCDS1 bit) is set to "0" during subclock selection or when standby control
register (STCR) bit 0 (OSCD1 bit) is set to "0" during main clock selection, stop mode is cleared and
the RUN state (normal operation) is entered.
To prevent stop mode from being cleared even when an interrupt request occurs, stop the main clock
oscillation stabilization wait timer or set the interrupt enable bit of the main clock oscillation
stabilization wait timer to interrupt disabled.
• Generation of a settings initialization reset (INIT) request
If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) is
unconditionally entered.
• Generation of an operation initialization reset (RST) request
If an operation initialization reset (RST) request occurs, the operation initialization reset (RST) is
unconditionally entered.
Note:
For information about the priority of sources, see "❍Priority of state transition requests" in Section
"3.11.1 Device States and State Transitions".
[Selecting a clock source in stop mode]
Select the main clock divided by 2 as the source clock before setting stop mode. For more information, see
Section "3.10 Clock Generation Control" especially Section "3.10.1 PLL Controls".
The same limitations as in the normal operation apply to the setting of a divide-by rate.
) as the interrupt level in the corresponding ICR.
) occurs, stop mode is
H
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