Clock Generation Control - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS
3.10

Clock Generation Control

This section describes clock generation control.
■ Generation of Internal Operating Clock
The internal operating clock of the MB91350A model type is generated as follows:
• Selection of a source clock: Select a clock supply source.
• Generation of a base clock:
• Generation of an internal clock:
The following describes generation and control of each clock.
For a detailed explanation of the registers and flags used in the explanation, see Section "3.10.5 Block
Diagram of Clock Generation Controller" and Section "3.10.6 Register of Clock Generation Controller".
■ Selection of Source Clock
The following describes source clock selection.
A resonator is connected to external oscillator pins X0/X1 and X0A/X1A, and the source oscillation
generated by the built-in oscillator circuit is used as the source clock.
The MB91350A model type is the source of all clocks, including the external bus clock.
The external oscillator pins and built-in oscillator circuit can use the main clock or subclock, and these two
clocks can be arbitrarily switched during operation.
• Main clock: The main clock, generated from the X0/X1 pins, is intended for use as a high-speed clock.
• Subclock:
The main clock and subclock are multiplied by the built-in main PLL and subclock, each of which can be
independently controlled.
Generate an internal base clock by selecting one of the following source clocks:
• Main clock divided by 2
• Main clock multiplied in the main PLL
• Subclock as is
Select a source clock by setting the clock source control register (CLKR).
104
Divide the source clock by two or perform PLL oscillation to generate a
base clock.
Divide the base clock and generate four types of operating clocks,
which are supplied to each section.
The subclock, generated from the X0A/X1A pins, is intended for use as a low-speed clock.