Structure Of The 16-Bit Free-Running Timer - Fujitsu FR60 Hardware Manual

7.1.1

Structure of the 16-bit Free-Running Timer

The 16-bit free-running timer consists of a 16-bit up counter and a control status
register.
• One of four count clocks can be selected.
• An interrupt can be generated for a counter overflow.
• The counter can be initialized on a match of the value for output compare register 0
when the mode setting allows the initialization.
■ 16-bit Free-running Timer Registers
The 16-bit free-running timer registers are shown below.
15 14
T15 T14
7 6
T07 T06
7 6
ECLK IVF
■ Block Diagram of the 16-bit Free-running Timer
Figure 7.1-1 shows a block diagram of the 16-bit free-running timer.
13 12 11
T13 T12 T11
5 4 3
T05 T04 T03
5 4 3
IVFE STOP MODE
Figure 7.1-1 Block Diagram of the 16-bit Free-running Timer
ECLK IVFE
IVF STOP
16-bit free-running timer
(TCDT)
10 9 8
T10 T09 T08 Timer data register (high-order bits)
2 1 0
Timer data register (low-order bits) (TCDT)
T02 T01 T00
2 1 0 Timer control status register
(low-order bits) (TCCS)
CLR CLK1 CLK0
Interrupt
CLR CLK1
MODE
Clock
To internal circuit (T15 to T00)
Comparator 0
CLK0
Freq.
divider
FRC K
Clock
selector
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