APPENDIX
Table D-12 Normal Branch (No Delay)
Mnemonic
JMP @Ri
CALL label12
CALL @Ri
RET
INT #u8
INTE
RETI
BRA label9
BNO label9
BEQ label9
BNE label9
BC label9
BNC label9
BN label9
BP label9
BV label9
BNV label9
BLT label9
BGE label9
BLE label9
BGT label9
BLS label9
BHI label9
Notes:
• "2/1" under CYCLE indicates 2 when branching occurs and 1 when branching does not occur.
• In the rel11 and rel8 fields of the hardware specifications, the assembler calculates values and sets them as shown below:
(label12-PC-2)/2 → rel11, (label9-PC-2)/2 → rel8; label12 and label9 have a sign.
• To execute the RETI instruction, the S flag must be 0.
610
Type
OP
CYCLE
E
97-0
2
F
D0
2
E
97-1
2
97-2
2
D
1F
3+3a
E
9F-3
3+3a
E
97-3
2+2a
DD
E0
2
D
E1
1
E2
2/1
DD
DD
E3
2/1
DD
E4
2/1
DD
E5
2/1
DD
E6
2/1
DD
E7
2/1
D
E8
2/1
E9
2/1
EA
2/1
EB
2/1
EC
2/1
ED
2/1
EE
2/1
EF
2/1
NZVC
Operation
→
----
Ri
PC
→
----
PC+2
RP ,
PC+2+(label12-PC-2)
→
→
----
PC+2
RP ,Ri
PC
→
----
RP
PC
→
CCCC
SSP-=4,PS
(SSP),
→
SSP-=4,PC+2
(SSP),
→
→
0
I flag,0
S flag,
(TBR+0x3FC-u8x4)
→
SSP-=4,PS
(SSP),
→
SSP-=4,PC+2
(SSP),
→
0
S flag,
→
(TBR+0x3D8)
PC
→
CCCC
(R15)
PC,R15-=4,
→
(R15)
PS,R15-=4
----
PC+2+(label9-PC-2)
----
No branch
----
if(Z==1) then
PC+2+(label9-PC-2)
↑ s/Z==0
----
↑ s/C==1
----
↑ s/C==0
----
↑ s/N==1
----
↑ s/N==0
----
↑ s/V==1
----
↑ s/V==0
----
↑ s/V xor N==1
----
↑ s/V xor N==0
----
↑ s/(V xor N) or Z==1
----
↑ s/(V xor N) or Z==0
----
↑ s/C or Z==1
----
↑ s/C or Z==0
----
Remarks
→
PC
Return
→
PC
For emulator
→
PC
→
PC