Detailed Explanation Of Registers - Fujitsu FR60 Hardware Manual

16.2

Detailed Explanation of Registers

This section describes the DMAC registers in detail.
■ Notes on Setting Registers
When the DMA controller (DMAC) is set, some bits need to be set while DMA is stopped. If they are set
while DMA is in progress (during transfer), correct operation cannot be guaranteed.
A marked bit indicates that the bit affects operation if it is set during DMAC transfer. Rewrite this bit while
DMAC transfer is stopped (start is disabled or temporarily stopped).
The setting of this bit that is made while DMA transfer start is disabled (when the DMAE bit of DMACR is
"0" or the DENB bit of DMACA is "0") becomes effective when DMA transfer start is enabled.
The setting of this bit that is made while DMA transfer is temporarily stopped (when the DMAH3 to
DMAH0 bits of DMACR are not 0000 or the PAUS bit of DMACA is "1") becomes effective when
temporary stop is canceled.
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