Overview Of The External Bus Interface - Fujitsu FR60 Hardware Manual
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CHAPTER 4 EXTERNAL BUS INTERFACE
4.1
Overview of the External Bus Interface
This section describes the features of the external bus interface.
■ Features of the External Bus Interface
•
Addresses of up to 32 bits can be output.
•
Various kinds of external memory (8-bit/16-bit modules) can be directly connected and multiple access
timings can be mixed and controlled.
•
Asynchronous SRAM and asynchronous ROM/FLASH memory (multiple write strobe method or
byte enable method)
•
Page mode ROM/FLASH memory (Page sizes 2, 4, and 8 can be used)
•
Address/data multiplex bus (8-bit/16-bit width only)
•
Synchronous memory (such as ASIC built-in memory)
Note: Synchronous SRAM cannot be directly connected.
•
Four independent banks (chip select areas) can be set, and chip select corresponding to each bank can
be output.
•
The size of each area can be set in multiples of 64K bytes (64K bytes to 2 GB for each chip select
area).
•
An area can be set at any location in the logical address space (Boundaries may be limited
depending on the size of the area.)
•
In each chip select area, the following functions can be set independently:
•
Enabling and disabling of the chip select area (Disabled areas cannot be accessed)
•
Setting of the access timing type to support various kinds of memory
•
Detailed access timing setting (individual setting of the access type such as the wait cycle)
•
Setting of the data bus width (8-bit/16-bit)
•
Setting for the order of bytes (big or little endian)
Note: Only big endian can be set for the CS0 area.
•
Setting of write disable (read-only area)
•
Enabling and disabling of fetches from the built-in cache
•
Enabling and disabling of the prefetch function
•
Maximum burst length setting (1, 2, 4, 8)
•
A different detailed timing can be set for each access timing type.
•
For the same type of access timing, a different setting can be made in each chip select area.
•
Auto-wait can be set to up to 15 cycles (asynchronous SRAM, ROM, Flash, and I/O area).
•
The bus cycle can be extended by external RDY input (asynchronous SRAM, ROM, Flash, and I/O
area).
•
The first access wait and page wait can be set (burst, page mode, and ROM/FLASH area).
•
Various kinds of idle/recovery cycles and setting delays can be inserted.
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