Fujitsu FR60 Hardware Manual page 602

APPENDIX
Table A-1 I/O Map (2 / 10)
Address
+0
000058
H
XXXXXXXXXXXXXXXX
00005C
H
SSR0[R/W]B,H,W
000060
H
00001000
UTIM0[R]H(UTIMR0[W]H)
000064
H
SSR1[R/W]B,H,W
000068
H
00001000
UTIM1[R]H(UTIMR1[W]H)
00006C
H
SSR2[R/W]B,H,W
000070
H
00001000
UTIM2[R]H(UTIMR2[W]H)
000074
H
ADCS2[R/W]B,H,W
000078
H
0000XX00
ADTH0[R]B,H,W
00007C
H
000000XX
ADTH2[R]B,H,W
000080
H
000000XX
000084
________
H
000088
________
H
________
00008C
H
________
000090
H
IBCR[R]B,H,W
000094
H
00000000
000098
H
00009C
________
H
________
0000A0
H
________
0000A4
H
0000A8
H
XXXXXXXXXXXXXXXX
0000AC
H
*1: This is a test register. Access is not allowed.
*3: The MB91F353A/351A/352A/353A do not have this register. Access is not allowed.
584
+1
TMRLR2[W]H,W
________
SIDR0[R]
SORR0[W]B,H,W
XXXXXXXX
0000000000000000
SIDR1[R]
SORR1[W]B,H,W
XXXXXXXX
0000000000000000
SIDR2[R]
SORR2[W]B,H,W
XXXXXXXX
0000000000000000
ADCS1[R/W]B,H,W
000X0000
ADTL0[R]B,H,W
XXXXXXXX
ADTL2[R]B,H,W
XXXXXXXX
DACR2[R/W]B,H,W
*3
-------0
DADR2[R/W]B,H,W
XXXXXXXX
________
________
IBSR[R]B,H,W
00000000
ITMK[R/W]B,H,W
0011111111111111
IDAR[R/W]B,H,W
*1
00000000
*1
________
*1
________
TMRLR3[W]H,W
________
Register
+2
TMR2[R]H,W
XXXXXXXXXXXXXXXX
TMCSR2[R/W]B,H,W
----000000000000
SCR0[R/W]B,H,W
00000100
DRCL0[W]B
--------
SCR1[R/W]B,H,W
00000100
DRCL1[W]B
--------
SCR2[R/W]B,H,W
00000100
DRCL2[W]B
--------
ADCT[R/W]H,W
XXXXXXXX_XXXXXXXX
ADTH1[R]B,H,W
000000XX
ADTH3[R]B,H,W
000000XX
DACR1[R/W]B,H,W
-------0
*3
DADR1[R/W]B,H,W
XXXXXXXX
________
________
ITBA[R/W]B,H,W
0000000000000000
ISMK[R/W]B,H,W
01111111
ICCR[R/W]B,H,W
00011111
________
*1
________
TMR3[R]H,W
XXXXXXXXXXXXXXXX
TMCSR3[R/W]B,H,W
----000000000000
+3
Reload timer 2
SMR0[R/W]B,H,W
UART0
00--0---
UTIMC0[R/W]B
U-timer/UART0
000001
SMR1[R/W]B,H,W
UART1
00--0---
UTIMC1[R/W]B
U-timer/UART1
000001
SMR2[R/W]B,H,W
UART2
00--0---
UTIMC2[R/W]B
U-timer/UART2
000001
ADTL1[R]B,H,W
A/D converter
XXXXXXXX
ADTL3[R]B,H,W
XXXXXXXX
DACR0[R/W]B,H,W
D/A converter
-------0
DADR0[R/W]B,H,W
D/A converter
XXXXXXXX
________
Reserved
*1
________
Reserved
ISBA[R/W]B,H,W
2
I C interface
00000000
IDBL[R/W]B,H,W
-------0
*1
________
Reserved
*1
________
Reload timer 3
Block
*3
*3