Tcr (Terminal And Timing Control Register) - Fujitsu FR60 Hardware Manual

CHAPTER 4 EXTERNAL BUS INTERFACE
4.2.6

TCR (Terminal and Timing Control Register)

This section describes the terminal and timing control register in detail.
■ Configuration of the Terminal and Timing Control Register (TCR)
The configuration of the TCR is shown below:
7
00000683
BREN PSUS PCLR
H
This register controls all functions related to the external bus interface controller, such as setting of shared
pin functions and timing control.
[Bit 7] BREN (BRQ input enable: BRQ enable)
This bit enables BRQ pin input and external bus sharing.
BREN
0
1
In the initial state (0), BRQ input is ignored.
When "1" is set, the bus is made open (control with high impedance) and BGRNT is activated ("L" level is
output) when the bus is ready to be made open after the BRQ input becomes "H" level.
[Bit 6] PSUS (Prefetch suspend: Prefetch SUSpend)
This bit controls temporary stopping of prefetch to all areas.
PSUS
0
1
If "1" is set, no new prefetch operation is performed before "0" is written. Since during this time the
contents of the prefetch buffer are not deleted unless the error to a prefetch buffer occurs, clear the prefetch
buffer using the PCLR bit function (bit 5) before restarting prefetch.
184
6 5 4 3
Reserved Reserved Reserved
No bus sharing by BRQ/BGRNT. BRQ input is disabled.
Bus sharing by BRQ/BGRNT. BRQ input is enabled.
Enable prefetch
Suspend prefetch.
Initial value
2 1 0 at INIT
RDW1 RDW0 00000000
BRQ input enable setting
Prefetch control
Access
at RST
0000xxxx
R/W
B B