Ordinary Bus Interface - Fujitsu FR60 Hardware Manual

4.5

Ordinary Bus Interface

For an ordinary bus interface, the two clock cycles required for both read access and
write access become the basic bus cycle.
■ Basic Timing (For Successive Accesses) (TYP[3:0]=0000
Figure 4.5-1 shows the basic timing for successive accesses.
READ
WRITE
• AS is asserted for one cycle in the bus access start cycle.
• A[23:0] continues to output the address of the location of the start byte in word/halfword/byte access
from the bus access start cycle to the bus access end cycle.
• If the W02 bit of the AWR[0:3] registers is "0", CS0 to CS3 are asserted at the same timing as AS. For
successive accesses, CS0 to CS3 are not negated. If the W00 bit of the AWR register is "0", CS0 to CS3
are negated after the bus cycle ends. If the W00 bit is "1", CS0 to CS3 are negated one cycle after bus
access ends.
• RD and WR0 to WR1 are asserted from the 2nd cycle of the bus access. Negation occurs after the wait
cycle of bits W15 of W12 for the AWR register is inserted. The timing of asserting RD and WR0 to
WR1 can be delayed by one cycle by setting the W01 bit of the AWR register to "1".
• For read access, D[31:0] is read when MCLK rises in the cycle in which the wait cycle ended after RD
was asserted.
• For write access, data output to D[31:0] starts at the timing at which WR0 to WR1 are asserted.
Figure 4.5-1 Basic Timing For Successive Accesses
MCLK
A[23:0]
AS
CSn
RD
D[31:16]
WRn
D[31:16]
,AWR=0008
B
#2
#1
#1
#2
#1 #2
)
H
205