Fujitsu FR60 Hardware Manual page 651

M
Main Clock
Wait Time after Switching From the Subclock to the
Main Clock ........................................ 107
Main Clock Oscillation Stabilization Wait Timer
Block Diagram of the Main Clock Oscillation
Stabilization Wait Timer...................... 149
Explanation of the Main Clock Oscillation
Stabilization Wait Timer Register ......... 150
Main Clock Oscillation Stabilization Wait Timer
Interrupt ............................................. 152
Operation of the Main Clock Oscillation Stabilization
Wait Timer ......................................... 153
Precautions on Using the Main Clock Oscillation
Stabilization Wait Timer...................... 154
Time Intervals for Main Clock Oscillation
Stabilization Wait Timer...................... 149
Main DMAC Function
Main DMAC Functions .................................... 472
Main DMAC Operation
Main DMAC Operations................................... 493
Major Function
Major Functions of the Interrupt Controller ........ 324
Manipulation
Manipulation of Arrays Other than Character-type
Arrays Using Character String Operation
Functions ............................................. 39
Mapping
Mapping of Interrupt Control Register (ICR) ........ 75
Mapping of the Stack to the Little-endian Area
............................................................ 40
Mapping of Variables with Initial Values ............. 38
Master Addressing
Master Addressing ........................................... 466
MCLK
MCLK and SYSCLK ......................................... 33
MD
Mode Pins (MD0 to MD2) .................................. 33
Memory
D-bus Memory .................................................. 34
DMA Fly-by Transfer (I/O -> Memory)
(TYP[3:0]=0000
IOWR=41 ) ....................................... 222
H
Memory Map
Memory Map............................................... 46, 66
Memory Map of Flash Memory......................... 535
Memory Space
Correspondence between the Memory Space Area and
Peripheral Resource Registers .............. 583
Minimum Effective Pulse Width
Minimum Effective Pulse Width of the DREQ Pin
Input. ................................................. 518
,AWR=0008 , and
B H
Mode 1
Example of System Construction
(Using Mode 1) ...................................407
Mode Pin
Mode Pins..........................................................92
Mode Pins (MD0 to MD2)...................................33
Mode Register
Mode Register (MODR)......................................92
MODR
Mode Register (MODR)......................................92
Monitor
Emulator and Monitor Debuggers ........................43
Multiply
Multiply & Divide Register .................................63
N
NC
Handling of NC and Open Pins ............................33
Negate Timing
Negate Timing of the DREQ Pin Input when a
Demand Transfer Request is Stopped
..........................................................518
NMI
Block Diagram of the External Interrupt and
NMI Controller....................................343
Details of the Registers for the External Interrupt and
NMI Controller....................................344
External Interrupt and NMI Controller
Registers.............................................342
Level Mask for Interrupt and NMI .......................74
NMI ................................................................349
NMI (Non Maskable Interrupt) ..........................336
NMI/Hold Suppress Level Interrupt Processing
..........................................................511
Operation of User Interrupt/NMI..........................86
NMI Controller Register
External Interrupt and NMI Controller
Registers.............................................342
No Error
Communication Error that Causes No Error ........467
No-coprocessor Trap
No-coprocessor Trap...........................................89
Non Maskable Interrupt
NMI (Non Maskable Interrupt) ..........................336
Non-detection
Non-detection of Errors.......................................42
Normal
Normal and Synchronous Standby Operations
..........................................................142
Normal Reset Operation ....................................102
Normal Access
Normal Access and Address/Data Multiplex
Access ................................................176
INDEX
633