Fujitsu FR60 Hardware Manual page 88

CHAPTER 3 CPU AND CONTROL UNITS
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Step trace trap
A step trace trap does not occur between the execution of a branch instruction with a delay slot and the
delay slot.
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Interrupt NMI
An interrupt /NMI is not accepted between the execution of a branch instruction with a delay slot and the
delay slot.
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Undefined instruction exception
An undefined instruction exception does not occur if there is an undefined instruction in the delay slot. If an
undefined instruction is in the delay slot, it operates as a NOP instruction.
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