Device States And State Transitions - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS
3.11.1

Device States and State Transitions

Figure 3.11-1 shows the state transitions of the device.
■ Device States
1 INTX pin = 0 (INIT)
2 INIT pin = 1 (clearance of INIT state)
3 End of oscillation stabilization wait time
4 Release from reset (RST) state
5 Software reset (RST)
6 Entry to sleep state (writing of instruction)
7 Entry to stop state (writing of instruction)
8 Interrupt
9 External interrupt not requiring a clock
10 Switching from main clock to subclock
(writing of instruction)
11 Switching from subclock to main clock
(writing of instruction)
12 Watchdog timer reset (INIT)
13 Entry to subclock sleep state
(writing of instruction)
*1 To switch the clock source between the main clock and subclock, change the status of Bits 1 and 0
*2 To stop (watch state) circuits other than the watch timer, set standby control register (STCR) bit 1
(OSCD2 bit) to 0 and bit 0 (OSCD1 bit) to 1 in the subclock operating state, then switch to stop mode
(simultaneous write enabled).
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Figure 3.11-1 Device States
Main clock mode
1
Main clock stop
9
1
Oscillation
stabilization
3
wait RUN
1
Main clock sleep
8
Subclock mode
1 8
Subclock sleep
3
1
Oscillation
stabilization
wait RUN
9
1
Subclock stop
(watch state *2)
(CLKS1 and CLKS0 bits) of the clock source register (CLKR) in the RUN state after oscillation of the
switch-destination clock has been stabilized.
Highest
Power-on
1
Lowest
Setting
initialization
reset (INIT)
2
Main clock
oscillation
1
stabilization wait reset
3
Program reset
(RST)
1
4
7 5
12
6
Main clock RUN
1
10
11
12
Subclock RUN
13
1
7 5
4
Program reset
(RST) 1
Subclock stop
(watch state *2)
Priority of state transition
requests
Settings initialization reset
(INIT) request
End of oscillation stabilization
wait time
Operation initialization reset
(RST) request
Interrupt request
Stop mode request
Sleep mode request