Fujitsu FR60 Hardware Manual page 322

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CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER

[Bit 13] MDSE (Mode Select)

This bit is used to select either the PWM mode in which continuous pulses are output or the one-shot

mode in which a single pulse is output.

[Bit 12] RTRG (Restart enable)

This bit enables a restart resulting from a software trigger or trigger input.

[Bits 11 and 10] CKS1 and CKS0 (Counter Clock Select)

These bits are used to select the count clock of the 16-bit down counter.

φ: Peripheral machine clock

[Bit 9] PGMS (PPG Output Mask Select)

Writing "0" into this bit allows PPG output to be masked to "0" or "1", regardless of mode, cycle, and

duty settings.

Table 8.2-1 lists the PPG output states when "1" has been written to the PGMS bit.

Table 8.2-1 PPG Output States when PGMS Bit is 1

For all-"H" output in ordinary polarity mode or all-"L" output in reverse polarity mode, specify the

same value in the cycle setting register and duty setting register in order to output the above mask value

with the polarity reversed.

PWM mode (initial value)

One-shot mode

Restart disabled (initial value)

Restart enabled

Ordinary polarity

Reverse polarity

φ (initial value)

Mb91350a series