Fujitsu FR60 Hardware Manual page 410

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CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE

[Bit 6] P (Parity)

This bit specifies that even or odd parity be added to perform data communication.

[Bit 5] SBL (Stop Bit Length)

This bit specifies the number of stop bits, which marks the end of a frame in asynchronous (start-stop

synchronization) communication.

[Bit 4] CL (Character Length)

This bit specifies the data length of one frame that is sent or received.

7-bit data can be handled only in normal mode (Mode 0) of asynchronous (start-stop

synchronization) communication mode. Use 8-bit data in multiprocessor mode (Mode 1) and CLK

synchronous communication mode (Mode 2).

[Bit 3] A/D (Address/Data)

This bit specifies the data format of a frame that is sent or received in multiprocessor mode (Mode 1) of

asynchronous (start-stop synchronization) communication mode.

[Bit 2] REC (Receiver Error Clear)

Write "0" to this bit to clear the error flags (PE, ORE, and FRE) in the SSR register.

Writing "1" to this bit has no effect. "1" is always read from this bit.

Even parity [initial value]

1 stop bit [initial value]

7 bits [initial value]

Data frame [initial value]

Address frame

Mb91350a series