Fujitsu FR60 Hardware Manual page 226

CHAPTER 4 EXTERNAL BUS INTERFACE
■ Auto-Wait Timing (TYP[3:0]=0000
Figure 4.5-4 shows the auto-wait timing.
Setting of the W15-12 bits (first wait cycles) of the AWR register enables 0-15 auto-wait cycles to be set.
In Figure 4.5-4 , two auto-wait cycles are inserted, making a total of four cycles for access. If auto-wait is
set, the minimum number of bus cycles is 2 cycles + (first wait cycles). For a write operation, the minimum
number of bus cycles may be still longer depending on the internal state.
208
,AWR=2008
B
Figure 4.5-4 Auto-Wait Timing
Basic cycle
MCLK
A[23:0]
AS
CSn
RD
D[31:16]
WRn
D[31:16]
)
H
Wait cycle