Fujitsu FR60 Hardware Manual page 412

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CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE

■ Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)

The bit configurations of the serial input data register (SIDR) and serial output data register (SODR) are

shown below.

Note: The MB91F353A/351A/352A/353A do not have SIDR ch4 and SODR ch4.

Address : ch0 000061

Address : Same as above

These registers are data buffer registers for sending and receiving.

If the data length is seven bits, bit 7 (D7) of SIDR and SODR contains invalid data. Accessing SIDR and

SODR when BDS = 1 switches the high-order and low-order data on the bus. As a result, it appears that bit

0 (D0) is ignored.

Write to the SODR register only while the TDRE bit of the SSR register is "1".

Writing to the register with this address means writing to the SODR register. Reading from the

Initial value

Mb91350a series