Clock Control Register (Iccr) - Fujitsu FR60 Hardware Manual

15.2.3

Clock Control Register (ICCR)

Clock control register specifies the enabled operation of I
frequency of serial clock.
■ Clock Control Register (ICCR)
The configuration of the clock control register (ICCR) is shown below.
Address : 00009E
Initial value→
[Bit 15] Test bit
Be sure to write "0" to it.
[Bit 14] Unused bit
Be sure to write "0" to it.
[Bit 13] EN (ENable)
This bit is the enable bit for the I
Value
0
1
When the EN bit is "0", all bits of the IBSR register and IBCR register (except for the BER and BEIE
bits) are cleared. A bus error clears this bit (BER = 1 in IBCR).
Note:
When operation is not allowed, the I
[Bit 12 to 8] CS4 to 0 (Clock Period Select 4 to 0)
These bits set the frequency of the serial clock.
These bits can be written only when the I
The frequency of the shift clock, fsck, is set as shown below.
fsck=
455
15 14
TEST -
H
W R R/W
0 0
2
C interface.
Disabled
Enabled
2
C interface immediately stops sending and receiving.
φ
N > 0
n × 12+16
2
C interface and the
13 12 11 10
EN CS4 CS3 CS2
R/W R/W R/W
0 1 1 1
Function
2
C interface is disabled (EN = 0) or the EN bit is cleared.
φ : Peripheral machine clock (= CLKP)
2
15.2 I C Interface Register
9 8
CS1 CS0
R/W R/W
1 1