Fujitsu FR60 Hardware Manual page 648
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- Hardware manual (636 pages) ,
- User manual (104 pages) ,
- User manual (26 pages)
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INDEX
2-Cycle Transfer (I/O -> External)
(TYP[3:0] = 0000
)...................................... 227
IOWR = 00
H
2-Cycle Transfer
(The Timing is the Same for Internal RAM
-> External I/O and RAM and for External
I/O and RAM -> Internal RAM.)
(TYP[3:0] = 0000
IOWR = 00
)...................................... 225
H
Accessing I/O Ports ............................................ 35
Basic Block Diagram of the I/O Port .................. 232
Block Diagram of the Serial I/O Interface (SIO)
.......................................................... 412
Configuration of the I/O Wait Registers for DMAC
(IOWR0 to IOWR3) ............................ 181
Control Signals on the Time Division I/O
Interface ............................................. 189
DMA Fly-by Transfer (I/O -> Memory)
(TYP[3:0] = 0000
IOWR = 51
)...................................... 213
H
DMA Fly-by Transfer (I/O -> Memory)
(TYP[3:0]=0000
) ....................................... 222
IOWR=41
H
DMA Fly-By Transfer (Memory -> I/O)
(TYP[3:0]=0000
IOWR=41
) ....................................... 223
H
DMA Fly-by Transfer (Memory -> I/O)
(TYP[3:0] = 0000
)...................................... 214
IOWR = 51
H
I/O Pins ........................................................... 165
I/O Ports.............................................................. 5
I/O Ports With Pull-up Resistors ........................ 232
Overview of Serial I/O Interface (SIO)
Operation ........................................... 419
Overview of the Serial I/O Interface (SIO).......... 410
Reading the I/O Map ........................................ 582
Serial I/O Interface (SIO) Registers.................... 411
Serial I/O Interface Operating Modes ................. 411
Serial I/O Prescaler Control Register (CDCR)
.......................................................... 417
Shift Operation Start/Stop Timing and I/O
Timing ............................................... 421
States of Serial I/O Interface Operation .............. 420
Transfer Between External I/O and External
Memory ............................................. 521
I/O Map
Reading the I/O Map ........................................ 582
I/O Port
Accessing I/O Ports ............................................ 35
Basic Block Diagram of the I/O Port .................. 232
I/O Wait Register
Configuration of the I/O Wait Registers for DMAC
(IOWR0 to IOWR3) ............................ 181
2
I
C
Block Diagram of the I
2
Features of I
C Interface ................................... 440
630
, AWR = 0008
, and
B
H
, AWR = 0008
, and
B
H
, AWR = 0008
, and
B
H
,AWR=0008
, and
B
H
, AWR=0008
, and
B
H
, AWR = 0008
, and
B
H
2
C Interface .................... 443
2
C Bus Interface (400 kbps Supported) ................. 5
I
2
C Interface Registers ..................................... 441
I
2
C Interface Registers ............. 444
Overview of the I
2
I
C Interface Register
2
I
C Interface Registers ..................................... 441
2
Overview of the I
C Interface Registers ............. 444
IBCR
Bus Control Register (IBCR) ............................ 448
IBSR
Bus Status Register (IBSR) ............................... 445
ICCR
Clock Control Register (ICCR) ......................... 455
ICR
Bit Configuration of the Interrupt Control Register
(ICR) ................................................. 329
Configuration of Interrupt Control Register (ICR)
........................................................... 75
Mapping of Interrupt Control Register (ICR) ........ 75
ICS
Input Capture Control Registers
(ICS01 and ICS23).............................. 428
IDAR
Data Register (IDAR)....................................... 462
IDBL
Clock Disable Register (IDBL) ......................... 463
If an External Pin Transfer Request is Reentered
If an External Pin Transfer Request is Reentered
During Transfer .................................. 521
If Another Transfer Request Occurs
If Another Transfer Request Occurs During Block
Transfer ............................................. 521
ILM
ILM.................................................................. 61
Interrupt Level Mask (ILM) Register ................... 74
INIT
INIT Pin Input (Settings Initialization Reset Pin)
........................................................... 96
Setting Initialization Reset (INIT) Clear
Sequence.............................................. 98
Settings Initialization Reset (INIT) ...................... 95
Initial Value
Initial Values and Functions of the Port Function
Registers (PFRs) ................................. 238
Mapping of Variables with Initial Values ............. 38
Initialization
INIT Pin Input (Settings Initialization Reset Pin)
........................................................... 96
Operation Initialization Reset (RST) .................... 95
Operation Initialization Reset (RST) Clear
Sequence.............................................. 98
Overview of Reset (Device Initialization)............. 94
Setting Initialization Reset (INIT) Clear
Sequence.............................................. 98
Settings Initialization Reset (INIT) ...................... 95
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