Fujitsu FR60 Hardware Manual page 318

CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER
■ Block Diagram of the PPG Timer (Overall Configuration and One Channel)
Figure 8.1-2 shows the overall block diagram of the PPG timer.
Figure 8.1-2 Block Diagram of the PPG Timer (Overall Configuration)
External TRG0 to TRG3
Note:
The MB91F353A/351A/352A/353A do not have PPG1, PPG3, PPG5, and external TRG5.
300
16-bit reload
timer channel 0
16-bit reload
timer channel 1
General control
register 20
4
External TRG4
External TRG5
TRG input
PPG timer channel 0
TRG input
General
PPG timer channel 1
control
register 10
(source selection)
TRG input
PPG timer channel 2
TRG input
PPG timer channel 3
TRG input
PPG timer channel 4
TRG input
PPG timer ch5
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5