Fujitsu FR60 Hardware Manual page 504

CHAPTER 16 DMA CONTROLLER (DMAC)
[Bit 19] EDIE (EnD Interrupt Enable): End interrupt output enable
This bit controls the occurrence of an interrupt for normal termination.
EDIE
• When reset: Initialized to "0".
• This bit is readable and writable.
[Bits 18 to 16] DSS2 to 0 (DMA Stop Status): Transfer stop source indication
These bits indicate a code (end code) of 3 bits that indicates the source of stopping or termination of
DMA transfer on the corresponding channel. The table below lists the end codes:
DSS
000
x01
x10
x11
1xx
The code indicating a transfer stop request is set only if the request is received from a peripheral circuit and
the external pin DSTP function is used.
Notes: • The MB91F353A/351A/352A/353A do not support the external pin DSTP function.
• When reset: Initialized to "000".
• These bits can be cleared by writing "000" to them.
• These bits are readable and writable. Note, however, that the only valid written value is "000".
[Bits 15 to 8] SASZ (Source Addr count SiZe): Transfer source address count size specification
These bits specify the increment or decrement width for the transfer source address (DMASA) of the
corresponding channel for each transfer operation. The value set by these bits becomes the address
increment/decrement width for each transfer unit. The address increment/decrement width conforms to
the instruction in the transfer source address count mode (SADM).
SASZ
XXXX
• When reset: Not initialized
• These bits are readable and writable.
486
0 Disables end interrupt request output. (initial value)
1 Enables end interrupt request output.
Initial value
Address error (underflow/overflow)
Transfer stop request
Normal end
DMA stopped temporarily (due, for example, to DMAH, PAUS bit,
and an interrupt)
• The Interrupt column indicates the type of interrupts that can occur.
Specify the increment/decrement width of the transfer source address. "0" to "255"
Function
Function
Function
Interrupt
None
Error
Error
End
None