Fujitsu FR60 Hardware Manual page 115

■ Software Reset (STCR: SRST Bit Writing)
If "0" is written to Bit 4 (SRST bit) of the standby control register (STCR), a software reset request occurs.
A software reset request is an operation initialization reset (RST) request.
When the request is accepted and a operation initialization reset (RST) is generated, the software reset
request is cleared.
If an operation initialization reset (RST) is generated due to a software reset request, a Bit 11 (SRST bit) in
the RSRR (reset source register) is set.
An operation initialization reset (RST) is generated due to a software reset request only after all bus access
has stopped and if Bit 7 (SYNCR bit) of the timebase counter control register (TBCR) has been set
(synchronization reset mode).
Thus, depending on the bus usage status, a long time is required before an operation initialization reset
(RST) occurs.
• Reset source: Writing "0" to Bit 4 (SRST) of the standby control register (STCR)
• Source of clearing: Generation of an operation initialization reset (RST)
• Reset level: Operation initialization reset (RST)
• Corresponding flag: Bit 11(SRST)
■ Watchdog Reset
Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Unless A5
written to the watchdog reset postpone register (WPR) within the cycle specified in Bits 9 and 8 (WT1 and
WT0 bits) in the RSRR, a watchdog reset request occurs.
A watchdog reset request is a settings initialization reset (INIT) request. If, after the request is accepted, a
settings initialization reset (INIT) occurs or an operation initialization reset (RST) occurs, the watchdog
reset request is cleared.
If a settings initialization reset (INIT) is generated due to a watchdog reset request, Bit 13 (WDOG bit) in
the reset source register (RSRR) is set.
Note that, if a settings initialization reset (INIT) is generated due to a watchdog reset request, the oscillation
stabilization wait time is not initialized.
• Reset source: Setting cycle of the watchdog timer elapses
• Source of clearing: Generation of a settings initialization reset (INIT) or an operation initialization
• Reset level: Settings initialization reset (INIT)
• Corresponding flag: Bit 13 (WDOG)
reset (RST)
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