Fujitsu FR60 Hardware Manual page 121

References:
• The DMA controller, which stops transfer when a request is accepted, does not delay transition to
another state.
• If Bit 7 (SYNCR bit) of the timebase counter control register (TBCR) is set to "1", synchronous
reset mode is selected.
The initial value after a settings initialization reset (INIT) is normal reset mode.
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