Fujitsu FR60 Hardware Manual page 601

■ Correspondence between the Memory Space Area and Peripheral Resource Registers
Table A-1 I/O Map (1 / 10)
Address
+0
000000
________
H
PDR4[R/W]B
000004
H
XXXXXXXX
PDR8[R/W]B
000008
H
--XXXXXX
PDRC[R/W]B
00000C
H
-----XXX
PDRG[R/W]B
000010
H
--XXXXXX
PDRK[R/W]B
000014
H
XXXXXXXX
PDRO[R/W]B
000018
H
XXXXXXXX
________
00001C
H
________
000020
H
SMCS5[R/W]B,H
000024
H
00000010----00--
SMCS6[R/W]B,H
000028
H
00000010----00--
SMCS7[R/W]B,H
00002C
H
00000010----00--
000030
________
H
CDCR6[R/W]B
000034
H
0---1111
000038
________
H
________
00003C
H
EIRR0[R/W]B,H,W
000040
H
00000000
DICR[R/W]B,H,W
000044
H
-------0
000048
H
XXXXXXXXXXXXXXXX
00004C
H
000050
H
XXXXXXXXXXXXXXXX
000054
H
*1: This is a test register. Access is not allowed.
*3: The MB91F353A/351A/352A/353A do not have this register. Access is not allowed.
+1
________
PDR5[R/W]B
XXXXXXXX
PDR9[R/W]B
---XXXXX
*3
________
*3
PDRH[R/W]B
--XXXXXX
PDRL[R/W]B
------XX
*3
PDRP[R/W]B
----XXXX
________
*3
________
*1
________
*3
SRCL5[W]B
--------
________
ENIR0[R/W]B,H,W
00000000
HRCL[R/W]B,H,W
0--11111
TMRLR0[W]H,W
________
TMRLR1[W]H,W
________
Register
+2
PDR2[R/W]B
XXXXXXXX
PDR6[R/W]B
XXXXXXXX
PDRA[R/W]B
----XXXX
PDRI[R/W]B
--XXXXXX
PDRM[R/W]B
--XXXXXX
________
________
*3
SES5[R/W]B
------00
SES6[R/W]B
------00
SES7[R/W]B
------00
*3
CDCR5[R/W]B
0---1111
CDCR7[R/W]B
0---1111
SRCL6[W]B
--------
________
ELVR0[R/W]B,H,W
00000000
________
TMR0[R]H,W
XXXXXXXXXXXXXXXX
TMCSR0[R/W]B,H,W
----000000000000
TMR1[R]H,W
XXXXXXXXXXXXXXXX
TMCSR1[R/W]B,H,W
----000000000000
APPENDIX A I/O Map
Block
+3
PDR3[R/W]B
XXXXXXXX
________
T-unit port data
*3
PDRB[R/W]B
register
XXXXXXXX
*3
PDRJ[R/W]B
XXXXXXXX
PDRN[R/W]B
R-bus port data
--XXXXXX
register
________
________
Reserved
*3
SDR5[R/W]B
*3
SIO5
XXXXXXXX
SDR6[R/W]B
SIO6
XXXXXXXX
SDR7[R/W]B
SIO7
XXXXXXXX
SIO
*1
________
prescaler 5
SIO
*1
________
prescaler 6, 7
SRCL7[W]B
SIO5 to 7
--------
________
Reserved
Extint
(INT0 to 7)
DLYI/I-unit
Reload timer 0
Reload timer 1
*3
*3
*3
*3
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