Fujitsu FR60 Hardware Manual page 447

[Bits 7 and 6] ICP3 to ICP0
These bits are used as input capture interrupt flags. When a valid edge of the signal input via an external
input pin is detected, "1" is written to the corresponding bits in ICP3 to ICP0. If the corresponding
interrupt enable bit (ICE3 to ICE0) is set, an interrupt can be generated when the valid edge is detected.
Writing "0" to the ICP3 to ICP0 bits clears them. Writing "1" to these bits is invalid. If a read modify
write instruction is issued, "1" is always read from each of these bits.
ICPn
0 Valid edge not detected (initial value)
1 Valid edge detected
"n" in ICPn indicates an input capture module channel number.
[Bits 5 and 4] ICE3 to ICE0
These bits are used to enable an input capture interrupt. If "1" is written to one of these bits, an input
capture interrupt is generated when "1" is written to the corresponding interrupt flag (ICP3 to ICP0).
ICEn
0 Interrupt disabled (initial value)
1 Interrupt enabled
"n" in ICEn indicates an input capture module channel number.
[Bits 3 to 0] EG31, EG30, EG21, EG20, EG11, EG10, EG01, and EG00
These bits are used to specify the valid edge polarity of external input. These bits are used also to enable
an input capture operation.
EGn1
0
0
1
1
"n" in EGn1 and EGn0 indicates an input capture module channel number.
Input capture interrupt flag
Input capture interrupt
EGn0
0 No edge detection (stop state; initial value)
1
Rising-edge detection
0
Falling-edge detection
1
Both-edge detection
Edge detection polarity
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