Fujitsu FR60 Hardware Manual page 501

[Bits 29 to 28] MOD (MODe): Transfer mode setting
These bits set the operating mode of the corresponding channel as listed in the table below.
MOD
00 Block/step transfer mode (initial value)
01 Burst transfer mode
10 Demand transfer mode
11 Setting disabled
• When reset: Initialized to "00".
• These bits are readable and writable.
Note: The MB91F353A/351A/352A/353A do not support demand transfer. Setting of the MOD bit to "10"
is not allowed.
[Bits 27 to 26] WS (Word Size): Transfer data width selection
These bits are used to select the transfer data width of the corresponding channel. Transfer operations
are repeated in units of the data width specified in this register for as many times as the specified count.
WS
00 Byte-width transfer (initial value)
01 Halfword-width transfer
10 Word-width transfer
11 Setting disabled
• When reset: Initialized to "00".
• These bits are readable and writable.
[Bit 25] SADM (Source-ADdr. Count-Mode select): Transfer source address count mode
This bit specifies the address processing of the transfer source address of the corresponding channel for
each transfer operation.
An address increment is added or an address decrement is subtracted after each transfer operation
according to the specified transfer source address count width (SASZ). When the transfer is completed,
the next access address is written to the corresponding address register (DMASA).
As a result, the transfer source address register is not updated until DMA transfer is completed.
To make the address always the same, specify "0" or "1" for this bit and set the address count width
(SASZ and DASZ) to "0".
SADM
0 Increments the transfer source address. (initial value)
1 Decrements the transfer source address.
• When reset: Initialized to "0".
• This bit is readable and writable.
Function
Function
specification
Function
483