Fujitsu FR60 Hardware Manual page 290

CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers
■ U-TIMER Control Register (UTIMC)
The bit configuration of the U-TIMER control register (UTIMC) is shown below.
Note:
The MB91F353A/351A/352A/353A do not have ch4.
UTIMC
ch0 Address : 00000067
ch1 Address : 0000006F
ch2 Address : 00000077
ch3 Address : 000000C7
ch4 Address : 000000CF
UTIMC controls the operation of the U-TIMER.
Be sure to use a byte transfer instruction to access this register.
[Bit 7] UCC1 (U-timer Count Control 1)
This bit controls the U-TIMER counting method.
UCC1
0
1
n is the setting value of UTIMR.
α is the cycle of the output clock for UART.
The U-TIMER can set a normal cycle, 2(n+1) as well as an odd-numbered division for the UART.
Set UCC1 to "1" to generate a cycle of 2n+3.
Examples:
1. UTIMR=5, UCC1=0 → Generation cycle =2n+2= 12 cycles
2. UTIMR=25, UCC1=1 → Generation cycle =2n+3= 53 cycles
3. UTIMR=60, UCC1=0 → Generation cycle =2n+2=122 cycles
Set UCC1 to 0 to use the U-TIMER as the interval timer.
[Bits 6, 5] (reserved)
These bits are reserved.
[Bit 4] UTIE (U-TIMER Interrupt Enable)
Note:
Always write "0" to this bit because the MB91350A has no U-Timer interrupt.
272
7 6
H
UCC1 -
H
R/W -
H
0 -
H
H
Normal operation α=2n+2 (initial value)
+1 mode α=2n+3
5 4 3 2
- UTIE UNDR CLKS
- R/W R/W R/W
- 0 0 0
Operation
1 0
UTST UTCR
R/W R/W Access
0 1 Initial value