Fujitsu FR60 Hardware Manual page 420

CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE
• SCR register
• PEN: 0
• P,SBL,A/D: These bits are meaningless.
• CL: 1
• REC: 0 (to initialize the register)
• RXE, TXE: At least one of the bits must be set to "1".
• SSR register
• RIE: Set to "1" to enable interrupts and to "0" to disables interrupts.
• TIE: 0
●
Start of communication
Write to the SODR register to start communication.
If only reception is performed, dummy send data must be written to the SODR register.
●
End of communication
Check for the end of communication by making sure that the RDRF flag of the SSR register has changed to
"1". Use the ORE bit of the SSR register to check that communication has been performed correctly.
■ Occurrence of Interrupts and Timing for Setting Flags
The UART has five flags and two interrupt sources.
The five flags are PE, ORE, FRE, RDRF, and TDRE. PE means parity error, ORE means overrun error,
and FRE means framing error. These flags are set when an error occurs during reception and are then
cleared when "0" is written to REC of the SCR register. RDRF is set when receive data is loaded into the
SIDR register and then cleared when data is read from the SIDR register. Mode 1 does not provide a parity
detection function. Mode 2 does not provide a parity detection function or a framing error function. TDRE
is set when the SODR register is empty, and writing to it is enabled and then cleared when data is written to
the SODR register.
There are two interrupt sources, one for receiving and the other for sending. During receiving, an interrupt
is requested due to PE, ORE, FRE, or RDRF. During sending, an interrupt is requested due to TDRE. The
following shows the timing for setting the interrupt flags in each of these modes.
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