Fujitsu FR60 Hardware Manual page 225

■ Write → Write Timing (TYP[3:0]=0000
Figure 4.5-3 shows the write → write timing.
MCLK
A[23:0]
AS
CSn
WRn
D[31:16]
• Setting of the W05/W04 bits of the AWR register enables 0-3 write recovery cycles to be inserted.
• After all of the write cycles, recovery cycles are generated.
• Write recovery cycles are also generated if write access is divided into phases for access with a bus
width wider than that specified.
,AWR=0018
B
Figure 4.5-3 Write → Write Timing
Read Write recovery
)
H
Write
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