Asr0 To Asr3 (Area Select Register) - Fujitsu FR60 Hardware Manual

CHAPTER 4 EXTERNAL BUS INTERFACE
4.2.1

ASR0 to ASR3 (Area Select Register)

This section describes the area select registers in detail.
■ Configuration of ASR0 to ASR3 (Area Select Registers)
The configuration of ASR0 to ASR3 is shown below:
ASR0
00000640
H
ASR1
00000644
H
ASR2
00000648
H
ASR3
0000064C
H
ASR4
00000650
H
ASR5
00000654
H
ASR6
00000658
H
ASR7
0000065C
H
The area select registers (ASR0 to ASR7) specify the start address of each chip select area for CS0 to CS7.
The start address can be specified in the 16 high-order bits from A31 to A16. Each chip select area starts
with the address set in this register and covers the range set by the four bits ASZ3 to ASZ0 of registers
ACR0 to ACR7.
The boundary of each chip select area obeys the setting for the four bits ASZ3 to ASZ0 of registers ACR0
to ACR7. For example, if an area of 1M bytes is set by the four bits ASZ3 to ASZ0, the four low-order bits
of registers ASR0 to ASR7 are ignored and only bits A31 to A20 are valid.
The ASR0 register is initialized to 0000
RST, and are therefore undefined. After starting chip operation, be sure to set the corresponding ASR
register before enabling each chip select area with the CSER register.
168
15 14 13 12
...
A31 A30 A29
15 14 13 12
...
A31 A30 A29
15 14 13 12
...
A31 A30 A29
15 14 13 12
...
A31 A30 A29
15 14 13 12
...
A31 A30 A29
15 14 13 12
...
A31 A30 A29
15 14 13 12
...
A31 A30 A29
15 14 13 12
...
A31 A30 A29
... 2 1 0 at INIT
...
0000
A18 A17 16
... 2 1 0
...
XXXX
A18 A17 16
... 2 1 0
...
XXXX
A18 A17 16
... 2 1 0
...
XXXX
A18 A17 16
... 2 1 0
...
XXXX
A18 A17 16
... 2 1 0
...
XXXX
A18 A17 16
... 2 1 0
...
XXXX
A18 A17 16
... 2 1 0
...
XXXX
A18 A17 16
by INIT and RST. ASR1 to 7 are not initialized by INIT and
H
Initial value
at RST Access
0000
R/W
H H
XXXX
R/W
H H
XXXX
R/W
H H
XXXX
R/W
H H
XXXX
R/W
H H
XXXX
R/W
H H
XXXX
R/W
H H
XXXX
R/W
H H