Input Capture Control Status Registers (Ics01, Ics23) - Fujitsu MB90895 Series Hardware Manual

7.3.3

Input capture control status registers (ICS01, ICS23)

The input capture control status registers sets the operation of input captures.The
ICS01 register sets the operation of input captures 0 and 1 and the ICS23 sets the
operation of input captures 2 and 3.The input capture control status registers provides
the following settings:
• Selecting the edge to be detected
• Enabling or disabling an interrupt when the edge is detected
• Checking and clearing the valid edge detection flag when the edge is detected
I Input capture control status registers (ICS01, ICS23)
Figure 7.3-4 Input capture control status registers (ICS01, ICS23)
7
R/W R/W
R/W
Numbers in ( ) show channel numbers in ICS23.
6
5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W
: Read/Write
: Reset value
Reset value
0 0 0 0 0 0 0 0
B
bit1 bit0
EG01 EG00 Input capture 0 (2) edge select bit
0 0 Without edge detection
0 1 Detect rising edge
1 0
Detect falling edge
1 1 Detect both edge
bit3 bit2
EG11 EG10 Input capture 1 (3) edge select bit
0 0 Without edge detection
0 1 Detect rising edge
1 0
Detect falling edge
1 1 Detect both edge
bit4
ICE0 Input capture 0 (2) interrupt enable bit
0 Input capture 0 (2) interrupt disable
1
Input capture 0 (2) interrupt enable
bit5
ICE1 Input capture 1 (3) interrupt enable bit
0
Input capture 1 (3) interrupt disable
1
Input capture 1 (3) interrupt enable
bit6
Input capture 0 (2) enable available edge detection flag bit
ICP0
Read
0 Input capture 0 (2)
without available edge detection
1 Input capture 0 (2)
With available edge detection
bit7
Input capture 1 (3) enable available edge detection flag bit
ICP1
Read
Input capture 1 (3)
0
without available edge detection
Input capture 1 (3)
1
With available edge detection
CHAPTER 7 16-bit I/O timer
Operating enable
Operating disable
Operating enable
Operating disable
Write
Clear of ICP0 bit
No effenct
Write
Clear of ICP1 bit
No effenct
233