16-Bit Reload Timer Register - Fujitsu FR60 Hardware Manual

7.2.2

16-bit Reload Timer Register

This section describes the configuration and functions of the registers used by the 16-
bit reload timer.
■ Control Status Register (TMCSR)
The bit configuration of the control status register (TMCSR) is shown below.
TMCSR
Address : 00004E
000056
00005E
0000AE
This register controls the 16-bit timer operation modes and interrupts.
Rewrite bits other than UF, CNTE, and TRG only when CNTE = 0.
Concurrent write to this register is allowed.
[Bit 13] Reserved
This bit is reserved. Be sure to set this bit to "0".
This bit is available only for ch3 except channels 0, 1, and 2.
[Bits 12, 11, and 10] CSL2, CSL1, CSL0 (Count source Select)
These bits are the count source select bits. Count sources can be selected from internal clocks and
external events. Table 7.2-1 shows the count sources that can be selected.
The count effective edges are set using the MOD1 and MOD0 bits when external events are specified
for count sources.
The CSL2 register is not available for the reload timer (ch0 to ch2). The CSL2 register is only available
for ch3, and up to divide-by 64 or 128 clock can be selected.
Table 7.2-1 Count Sources Set Using the CSL Bits
CSL2
0
0
0
0
1
1
Settings not listed in the table above are prohibited. The CSL2 bit is not available for channels 0 to 2.
15 14 13
- -
H
(Reserved)
H
- - (R/W)
H
H
7 6 5
OUTL
-
Reserved
R/W R R/W
CSL1 CSL0
0 0
0 1
1 0
1 1
0 1
1 0
12 11 10
(CSL2) CSL1 CSL0
Reserved
(R/W) R/W R/W
4 3 2
RELD INTE UF CNTE
R/W R/W R/W
Count source (φ: machine clock)
Internal clock φ/2 1
(ch0 to ch3)
Internal clock φ/2 3
(ch0 to ch3)
Internal clock φ/2 5
(ch0 to ch3)
Setting prohibited (ch0 to ch3)
Internal clock φ/2 6
(ch3 only)
Internal clock φ/2 7
(ch3 only)
9 8 Initial value
----0000 00000000
Reserved
R/W R/W
1 0
TRG
R/W R/W
B
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