Fujitsu FR60 Hardware Manual page 203

[Bit 5] PCLR (Prefetch buffer all clear: Prefetch buffer CleaR)
This bit completely clears the prefetch buffer.
PCLR
0 Normal state
1 Clear the prefetch buffer.
If "1" is written, the prefetch buffer is cleared completely. When clearing is completed, the bit value
automatically returns to "0". Interrupt (set to "1") the prefetch by the PSUS bit and then clear the buffer (It
is also possible to write 11
[Bits 4 to 2] Reserved (Reserved bit)
This bits are reserved. Be sure to set it to "0".
[Bits 1 to 0] RDW[1:0] (Wait cycle reduction: ReDuce Wait cycle)
These bits instruct all chip select areas and fly-by I/O channels to reduce only the number of auto-wait
cycles in the auto-access cycle wait settings uniformly while the AWR register settings are retained
unchanged. The settings for idle cycles, recovery cycles, setup cycles, and hold cycles are not affected.
These bits are not functional for the SDRAM control area.
RDW1 RDW0
0 0
0 1
1 0
1 1
The purpose of this function is to prevent an excessive access cycle wait during operation on a low-speed
clock (for example, when the base clock is switched to low speed or the frequency division ratio setting of
the external bus clock is large).
To reset the wait cycle in these cases, each of the AWRs must usually be rewritten one at a time. However,
when the RDW1/0 bit function is used, the access cycle wait is reduced for all of the AWRs in a single
operation while all of the other high-speed clock settings in each register are retained.
Before returning the clock to high speed, be sure to reset the RDW1/0 bits to 00
Prefetch buffer control
to both the PSUS and PCLR bits).
B
Normal wait (AWR0-7 settings)
1/2 (1-bit shift to the right) of the AWR0 to 3 settings
1/4 (2-bit shift to the right) of the AWR0 to 3 settings
1/8 (3-bit shift to the right) of the AWR0 to 3 settings
Wait cycle reduction
.
B
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