Fujitsu FR60 Hardware Manual page 16

Page
48 3.1 Memory Space
174 4.2.2 ACR0 to ACR7
(Area Configuration Reg-
isters)
230 4.10 Procedure for Setting
a Register
238 5.2 I/O Port Registers
to
244
246 6.1 8/16-bit Up/Down
Counters/Timers
271 6.2.2 U-TIMER Registers
275 6.2.3 Operation of the U-
TIMER
348 10.3 Operation of the
External Interrupt and
NMI Controller
384 13.3 8-bit D/A Converter
Operation
413, 414 14.2.2 Serial I/O Interface
Registers
450 15.2.2 Bus Control Regis-
ter (IBCR)
451
to
454
479 16.2.1 DMAC ch0 to ch4
Control/Status Registers A
Changes (For details, refer to main body.)
"■ Memory Map" was changed.
(For the MB91V350A, a 512K-byte internal ROM area is used as emulation
RAM for the MB91355A, F355A, 353A, and F353A memory map. In addi-
tion, the instruction internal RAM is extended from 8 KB to 16 KB. → For the
MB91V350A, with the memory map of the MB91355A/F355A/353A/F353A/
F357B, the 512K bytes area of the internal ROM, and with the memory map of
the MB91F356B, the 256K bytes area of the internal ROM, is the emulation
RAM. In addition, internal RAM(Instruction) is extended from 8K bytes to16K
bytes.)
"Notes:" was changed.
"(Set both ASR and ACR at the same time using word access. When accessing
ASR and ACR using half word, please set ACR after setting ASR.)" was
added.
"■ Procedure for Setting the External Bus Interface" was changed.
"Table 5.2-1 Initial Values and Functions of the Port Function Registers
(PFRs)" was changed.
("*2" was deleted.)
"■ Overview of the 8/16-bit Up/Down Counters/Timers" was changed.
(The MB91F355A/355A/354A/V350A→ The MB91F355A/355A/354A/
F356B/F357B)
"■ Reload Register (UTIMR)" was changed.
("Note:" was added.)
"■ Calculation of Baud Rate" was changed.
("Note:" was added.)
"■ Operating Procedure for an External Interrupt" was changed.
("1. Terminal and general-purpose I/O port used as external interrupt input are
set to input port." was added.)
"Table 13.3-1 Logical Expressions for D/A Converter Output Voltage" was
changed.
(Values specified in DADR1 DADR2 DADR3 → Values specified in DADR0
DADR1 DADR2)
"[Bits 15, 14, and 13] Shift clock selection bits (SMD2, SMD1, SMD0: Serial
shift clock mode)" was changed.
"[Bit 12] MSS (Master Slave Select)" was changed.
("Note:" was changed.)
"■ Bus Control Register (IBCR)" was changed.
("Note:" was changed.)
"■ [Bits 28 to 24] IS4 to 0 (Input Select)*: Transfer Source Selection" was
changed.
xii