Fujitsu FR60 Hardware Manual page 79

■ ILM
The configuration of the ILM register is shown below:
The interrupt level mask (ILM) register holds an interrupt level mask value. The value held in ILM is used
as a level mask.
An interrupt request to the CPU is accepted only when its interrupt level is higher than the level indicated
in this ILM.
The highest level is 0 (00000
The program setting range is limited.
• When the original value is between 16 and 31:
A new value between 16 and 31 can be set. If an instruction that sets a value between 0 and 15 is
executed, the specified value plus 16 is transferred.
• When the original value is between 0 and 15: Any value between 0 and 31 can be set.
Reset initializes this bit to 15 (01111
■ PC (Program Counter)
The configuration of the program counter (PC) register is shown below:
[Bits 31 to 0]
These are the bits of the program counter that indicates the address of the instruction being executed.
Bit 0 is set to "0" when the PC is updated after an instruction is executed. Bit 0 can become "1" only if
the branch address is an odd number address.
However, even if the branch address is an odd number address, bit 0 is invalid and therefore the
instruction should be placed at an address for multiple of two.
The initial value after reset is undefined.
■ TBR (Table Base Register)
The configuration of the table base register (TBR) is shown below:
The table base register holds the first address of the vector table to be used during EIT processing.
The initial value after reset is 000FFC00
20 19 18
ILM4 ILM3 ILM2
), and the lowest level is 31 (11111
B
).
B
31
PC
31
TBR
17 16 [Initial value]
01111
ILM1 ILM0
B
0 [Initial value]
XXXXXXXX
0 [Initial value]
000FFC00
.
H
B
).
H
H
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